The data are logic signals on the "0" or "1" level. The "0" level is theoretically defined as corresponding to a voltage equal to zero Volt, while the "1" level is defined as corresponding to a voltage equal to the logic supply voltage Vdd (about 5 Volts). However, in practice, for example in the field of NMOS (N channel metal oxide semiconductor technology), level "0" is a voltage comprised between 0 and a threshold voltage Vt of the channel N MOS transistors included in the circuit, while the level "1" may be a voltage comprised between Vt and 5 Volts.
It can be observed that in most cases, especially in the field of NMOS technology, the driving stages of the bus and the data receiving member are arranged in such a manner that inducing a conductor of the bus to pass from the "1" state to the "0" state can be effected far more rapidly than inducing such conductor to pass from the "0" state to the "1" state.
For this reason, and with a view to increasing the data output rate on the bus, a circuit for preloading the bus conductors has been provided in many cases, which circuit brings all the conductors to a potential level just sufficient to define the "1" state, or substantially to define said "1" state, during the first step, or transfer preparation step, since the duration of this step is anyway longer than that of the second step (transfer step proper), said first step corresponding, for example, to the execution of the calculations the result of which constitutes the data to be transmitted; in the second step (execution of the transfer) the conductors which must pass from the "1" state are already -or are substantially already- in said "1" state, while the conductors which should pass to the zero state will reach the same rapidly. Thus the second step of the cycle may have a minimum duration corresponding to the lapse of time required for a conductor to pass from the "1" state to the "0" state, which lapse of time can be very short.
FIG. 1 shows the arrangement of a preloaded data transfer system: the data emitting member is designated by reference ED and supplies data d1, d2, d3, d4 adapted to be transferred respectively to conductors c1, c2, c3, c4 of data transfer bus, with a view to being transmitted to a data receiving member RD.
A driving stage DR of the bus is interposed between the data output terminals of the emitting member ED and the bus conductors. This driving stage comprises, for example, for each conductor one AND gate receiving a data output and a transfer control signal, as well as a MOS transistor controlled by said gate and adapted to connect the corresponding conductor to the ground, or to isolate said conductor with respect to the ground, depending on the state of the output terminal of said AND gate.
The transfer control signal is at logic level "1" during the transfer step b (second step) of each data transmission cycle.
Furthermore a preloading circuit PR controlled by a preloading control signal at level "1" during the preloading step a (first step) of each cycle allows each bus conductor to be preloaded so as to bring it approximately to logic state "1". Step a and step b are distinct from each other or are strictly complementary.
In one arrangement according to the prior art, shown in FIG. 1, the preloading circuit comprises for each bus conductor to be preloaded three channel N MOS transistors connected in series between the ground and a general positive supply voltage Vdd. The conductor to be preloaded is connected between the second transistor and the third transistor (the latter being also connected to Vdd and receiving at its gate the preloading control signal a); the first and second transistors have their respective gates connected to their drain.
In this circuit arrangement the third transistor, from the very start of the preloading step a, is getting conductive and starts loading the capacity (which may be or not be a parasite capacity) defined by the conductor that is statically in a state of high impedance, at its input terminals as well as at its output terminal. In order that the loading can be effected rapidly, i.e. in order that the conductor reaches rapidly a predetermined preloading voltage, the third transistor should preferably be of a comparatively large size. When the voltage of the conductor reaches 2Vt, i.e. the sum of the threshold voltages of the first and second transistors, respectively, the latter will become conductive and stabilize the bus conductor preload voltage at a value of 2Vt. From this moment on, the preloading process is terminated.
When step a has been accomplished the third transistor will get blocked, and the bus conductors remain in the preloaded state. During step b, the data are applied through the driving stage.
The main drawback of this preloading circuit resides in the fact that between the instant when the bus conductor reaches the specified preloading voltage (2Vt in the example shown; another value might be selected, for instance Vt, or 3Vt, etc . . . ) and the end of the preloading step a great amount of current is consumed, since all three transistors are conductive. If the bus conductor had already been at level "1", this current consumption occurs during the entire preloading step. Given a bus having 32 conductors, this would result in 32 groups of simultaneously conductive transistors, thus involving a power consumption which may be very important, whereas it is attempted generally to reduce by any imaginable means the current consumption of the circuits.